1. Field of the Invention
The present invention relates to a traffic priority control system for a concentration-type ATM (Asynchronous Transfer Mode) switch which is used in an ATM exchange, an ATM cross-connect apparatus, or the like, and more particularly to an ATM concentrator for achieving traffic priority control while preventing a reduction in the throughput of transmitted cells of low priority class with a plurality of output cell buffers for priority classes.
2. Description of the Prior Art
For ATM communications, an information signal such as an audio, video, or data signal is digitized and stored in the payload of an ATM cell that is 53 bytes long, and an ATM traffic composed of the ATM cells is transmitted.
Audio, video, and data signals have different information rates (i.e., transmission bands) and different allowable transmission delay times. Therefore, users of these signals pose different requirements for the qualities of services (QoS) of ATM networks, such as transmission band assurances and transmission delay assurances, with respect to audio, video, and data traffic. For example, users want to reduce any transmission delay for audio and video traffic because if the transmission delay were too large, audio and video signals reproduced from ATM cells at a receiver would be unnatural to the users. On the other hand, low-rate data traffic keep their qualities from being lowered even when their transmission delay is somewhat large.
There is known a priority control system for controlling the transmission of information signals depending on a number of quality classes established with respect to different requirements for transmission delays and transmission bands of the information signals. According to the priority control system there are established, more specifically, quality classes for traffic comprising ATM cells of information signals, and one of the quality classes is assigned to an ATM cell depending on connection numbers such as VPI (Virtual Path Identifier) and VCI (Virtual Connection Identifier) and a CLP (Cell Loss Priority) bit that are contained in the header of the ATM cell. In a buffer of an ATM exchange or an ATM cross-connect, the quality class of the ATM cell for a connection is determined depending on the VPI, the VCI, and the CLP bit in the header of the arrived ATM cell, and the ATM cell is controlled for transmission depending on the determined quality class.
One example of such a priority control system will be described below with reference to FIG. 1. FIG. 1 shows an ATM cell buffer system having a single input highway and a single output highway. There are established two quality classes with respect to transmission delays, i.e., a high priority class (class 1) and a low priority class (class 2) for ATM cells. The ATM cell buffer system has a cell buffer 33 for storing ATM cells of the high priority class and a cell buffer 34 for storing ATM cells of the low priority class. The cell buffers 33, 34 are connected to the input highway through respective connection filters 31-1, 31-2. The connection filters 31-1, 31-2 refer to the VPI, the VCI, and the CLP bit of each ATM cell that has arrived from the input highway to determine the quality class of each ATM cell, and transfers valid cells of determined quality classes to the respective cell buffers 33, 34. For example, if an ATM cell that has arrived at the connection filter 31-1 is of the high priority, then the connection filter 31-1 stores the ATM cell in the cell buffer 33, and if an ATM cell of the low priority has arrived, then the connection filter 31-2 stores the ATM cell in the cell buffer 34. The cell buffers 33, 34 have respective output terminals connected to a readout controller 32 which reads ATM cells from the cell buffers 33, 34.
According to a process of determining a sequence to read ATM cells in the readout controller 32, as disclosed in Japanese laid-open patent publication No. 4-220834 (JP, A, 04220834) (column 7, lines 9 to 14), for example, the readout controller 32 attempts to read ATM cells from the cell buffer 33 for the high priority class, and if the number of ATM cells stored in the cell buffer 33 is zero, then the readout controller 32 attempts to read ATM cells from the cell buffer 34 for the low priority class. Such a process is referred to as full priority control. The full priority control is advantageous in that it allows the readout controller 32 to carry out a simple control process and is applicable to high-speed circuits.
An ATM concentrator will be described below. An ATM concentrator is an ATM switch for connecting a plurality of input highways to a fewer number of output highways than the input highways. An (mxc3x97nxe2x88x92n) ATM concentrator connects (mxc3x97n) input highways to n output highways. For example, as disclosed in Japanese laid-open patent publication No. 7-66827 (JP, A, 07066827) (see FIG. 1 thereof), if an ATM exchange or an ATM cross-connect which has (mxc3x97n) input highways and (mxc3x97n) output highways is to be constructed with m basic modules having n input highways and n output highways and a single connection module, an (mxc3x97nxe2x88x92n) ATM concentrator is used for connecting (mxc3x97n) input highways to n output highways in the connection module.
FIG. 2 shows a conventional (mxc3x97nxe2x88x92n) ATM concentrator. An (mxe2x88x921) selector serves to select one of m highways, and n pieces of (mxe2x88x921) selectors 11-1 to 11-n are connected to (nxc3x97m) input highways. A counter 12 is connected to control the (mxe2x88x921) selectors 11-1 to 11-n to select one of the input highways. Output signals from the (mxe2x88x921) selectors 11-1 to 11-n are supplied through respective connection filters 36-1 to 36-n to a routing decision circuit 13. The routing decision circuit 13 has output terminals connected to a routing network 14 of an (nxc3x97n) Banyan switch. The routing network 14 has n output terminals connected through respective output cell buffers 35-1 to 35-n, each comprising an FIFO (First-In First-Out) memory, to n output highways.
Input signals from the (nxc3x97m) input highways are multiplexed into n signals, whose speed is m times the speed of the input signals, by the (mxe2x88x921) selectors 11-1 to 11-n. Specifically, if the speed of an input signal from an input highway is represented by V, then the speed of a signal outputted from an (mxe2x88x921) selector is represented by mV. Based on a signal generated by the counter 12, the (mxe2x88x921) selectors 11-1 to 11-n are operated in synchronism each other for synchronized multiplex timing. The n multiplexed signals are delivered to the connection filters 36-1 to 36-n, respectively, which refer to the VPI, the VCI, or the CLP bit in the header of each ATM cell to decide whether the ATM cell is a valid cell of a passing connection to pass through the ATM concentrator or not. If the ATM cell is a valid cell of a passing connection, then the connection filters 36-1 to 36-n send the valid cell to the routing decision circuit 13. If the ATM cell is not of a passing connection or it is an invalid cell of a passing connection, then the connection filters 36-1 to 36-n write the ATM cell over an idle cell or an invalid cell.
The routing decision circuit 13 and the routing network 14 serve to hold sequences of arrival of valid cells from the same input highways and store valid cells uniformly in the output cell buffers 35-1 to 35-n for thereby preventing valid cells from concentrating on and hence overflowing some of the output cell buffers 35-1 to 35-n. Based on the known function of the Banyan switch for sorting a monotonous signal string into a continuous signal string without blocking, the routing decision circuit 13 and the routing network 14 shift and output valid cells, one by one, successively from highways of smaller numbers, and shift effective cells arriving in a next cell slot from a highway represented by the sum of 1 and the maximum highway number of the highway which has outputted valid cells in a preceding cell slot. When the highway number reaches its maximum value n, the routing decision circuit 13 and the routing network 14 control the highway number to go back to the first highway. Idle cells and invalid cells are outputted to a highway which is free of valid cells. A j-th highway will hereinafter be represented by xe2x80x9cHWjxe2x80x9d.
If four valid cells are simultaneously inputted to odd-numbered highways HW1, HW3, HW5, HW7 of the routing decision circuit 13 when n=8, then the routing network 14 outputs valid cells at the highways HW1, HW2, HW3, HW4. If seven valid cells are simultaneously inputted to the routing decision circuit 13 in a next cell slot, then the routing network 14 outputs valid cells at the highways HW5, HW6, HW7, HW8, HW1, HW2, HW3. The routing network 14 transmits ATM cells at a speed mV which is m times the input signal speed V to the output cell buffers 35-1 to 35-n, each of which stores m ATM cells in one cell slot. The output cell buffers 35-1 to 35-n store input cells even when they are idle cells or invalid cells other than valid cells. ATM cells are read from the cell output positions of the output cell buffers 35-1 to 35-n in each cell slot. Even if cells stored in the output cell buffers 35-1 to 35-n are idle cells or invalid cells, they are read from the output cell buffers 35-1 to 35-n.
FIG. 3 shows a conventional ATM concentrator for carrying out the full priority control with quality classes established. The ATM concentrator shown in FIG. 3 is similar to the ATM concentrator shown in FIG. 2 except that a high priority class (class 1) and a low priority class (class 2) are established with respect to transmission delays for full priority control. A cell stream from (nxc3x97m) input highways is supplied simultaneously to a sorting unit 1 for the high priority class and a sorting unit 2 for the low priority class. Each of the sorting units 1, 2 serves to concentrate the (nxc3x97m) input highways to n output highways. The sorting unit 1 for the high priority class has n output terminals connected respectively to output cell buffers 3-1 to 3-n for the high priority class. The numbers of valid cells stored in the output cell buffers 3-1 to 3-n are held by a valid cell number table 4. Similarly, the sorting unit 2 for the low priority class has n output terminals connected respectively to output cell buffers 6-1 to 6-n for the low priority class. The numbers of valid cells stored in the output cell buffers 6-1 to 6-n are held by a valid cell number table 7. A selector 39 serves to select n out of 2n highways from the output cell buffers 3-1 to 3-n, 6-1 to 6-n. A readout controller 38 refers to the valid cell number tables 4, 7 to control the reading of cells in the selector 39.
An example of each of the sorting units 1, 2 is shown in FIG. 4. The sorting unit shown in FIG. 4 is similar to a block 37, indicated by the dotted lines, of the ATM concentrator shown in FIG. 2 except that the connection filters 36-1 to 36-n shown in FIG. 2 are replaced with connection quality class filters 15-1 to 15-n which function as both connection filters and quality filters. The connection quality class filters 15-1 to 15-n refer to the VPI, the VCI, or the CLP bit in the header of each ATM cell to decide whether the ATM cell is an valid cell of a passing connection to pass through the sorting unit or not. If the ATM cell is an valid cell of a passing connection, then the connection quality class filters 15-1 to 15-n determines the quality class of the valid cell, i.e., decides whether the quality class is the class 1 or the class 2, based on the VPI, the VCI, or the CLP bit. If the ATM cell is an valid cell of the quality class to pass through the sorting unit 1 or 2, then the connection quality class filters 15-1 to 15-n send the valid cell to the routing decision circuit 13. If the ATM cell is not of a passing connection or it is an invalid cell of a passing connection, or if it is a valid cell of a passing connection but is not of the quality class to pass through the sorting unit, then the connection quality class filters 15-1 to 15-n write the ATM cell over an idle cell or an invalid cell. Consequently, the ATM concentrator shown in FIG. 3 selects ATM cells having predetermined VPI, VCI, and CLP bit and a predetermined quality class from input signals supplied from the (nxc3x97m) input highways, and supplies the selected ATM cells to the n highways. The ATM concentrator outputs ATM cells at a speed which is m times the speed at which they are inputted to the ATM concentrator.
Operation of the (mxc3x97nxe2x88x92n) ATM concentrator shown in FIG. 3 which has the full priority control capability will be described below. When ATM cells arrive at the ATM concentrator, the sorting units 1, 2 sort, for respective quality classes, those ATM cells having predetermined VPI, VCI, and CLP bit. If ATM cells are valid cells of the high priority class, then they are sorted by the sorting unit 1, and stored in the output cell buffers 3-1 to 3-n for the high priority class at a speed which is m times the speed at which the ATM cells are inputted. Likewise, if ATM cells are valid cells of the low priority class, then they are sorted by the sorting unit 2, and stored in the output cell buffers 6-1 to 6-n for the low priority class at a speed which is m times the speed at which the ATM cells are inputted.
The number of valid cells among a total of n ATM cells to be read from the output cell buffers 3-1 to 3-n at a next readout time is counted and written in the valid cell number table 4 for the high quality class. Similarly, the number of valid cells among a total of n ATM cells to be read from the output cell buffers 6-1 to 6-n at a next readout time is counted and written in the valid cell number table 7 for the low-quality class.
The selector 39 reads ATM cells, one by one, from the cell output positions of the output cell buffers 3-1 to 3-n for the high-quality class in each output selector slot. At the same time, the readout controller 38 reads the number of valid cells among ATM cells at the cell output positions of the output cell buffers 3-1 to 3-n from the valid cell number table 4. The readout controller 38 checks if the number of valid cells of the high priority class is 0 or not. If the number of valid cells of the high priority class is 1 or more, then the readout controller 38 outputs a select signal to the selector 39 to output n pieces of the ATM cells read from the output cell buffers 3-1 to 3-n. If the number of valid cells of the high priority class is 0, then the readout controller 38 outputs a select signal to the selector 39 to output ATM cells from the output cell buffers 6-1 to 6-n for the low quality class.
Therefore, if a select signal received from the readout controller 38 represents the selection of the class 1 (high priority class), then the selector 39 outputs the n ATM cells read from the output cell buffers 3-1 to 3-n for the high quality class, one by one, to the n output highways. If a select signal received from the readout controller 38 represents the selection of the class 2 (low priority class), then the selector 39 reads ATM cells from the cell output positions of the output cell buffers 6-1 to 6-n for the low quality class, and outputs n ATM cells, one by one, to the n output highways.
The conventional ATM concentrator shown in FIG. 3 is disadvantageous in that if the n ATM cells read from the output cell buffers 3-1 to 3-n for the high priority class which corresponds to a high quality class include even one valid cell, then the ATM concentrator does not output any ATM cells of a quality class lower than the high quality class, with the result that the throughput of the ATM concentrator will not increase. This is because when ATM cells arrive at such an interval that k valid cells (k is an integer in the range of 1xe2x89xa6k less than n) are always stored in any of the output cell buffers 3-1 to 3-n for the high priority class, the k valid cells are outputted from only the output cell buffers 3-1 to 3-n, but valid cells of the class 2 stored in the output cell buffers 6-1 to 6-n are not outputted at all, and idle cells and invalid cells are outputted from (nxe2x88x92k) of the output highways of the ATM concentrator whereas valid cells are transmitted through k highways.
For example, when ATM cells arrive at such an interval that while valid cells of the class 2 arrive highly frequently at the ATM concentrator, valid cells of the class 1 arrive less frequently at the ATM concentrator though one valid cell of the class 1 is always stored in any one of the output cell buffers 3-1 to 3-n, valid cells are outputted from only the output cell buffers 3-1 to 3-n, but any valid cells of the class 2 stored in the output cell buffers 6-1 to 6-n are not outputted at all, and idle cells and invalid cells are outputted from (nxe2x88x921) of the output highways of the ATM concentrator whereas valid cells are transmitted through only one highway. As a result, the utilization factor of the highways does not increase, and the throughput of the ATM concentrator does not increase.
It is, therefore, an object of the present invention to provide an ATM concentrator of an (mxc3x97nxe2x88x921) configuration which has output cell buffers assembled together into as many groups as the number of quality classes established for ATM cells, for carrying out full priority control for outputting valid cells of a higher priority class in preference to valid cells of a lower priority class, the ATM concentrator being capable of multiplexing and outputting valid cells of both the higher and lower priority class when the number of valid cells of the higher priority class in n output highways is small, for thereby increasing the utilization factor of the highways and the ATM concentrator throughput.
According to the present invention, the above object can be accomplished by an ATM concentrator having (mxc3x97n) input highways and n output highways and established CL quality classes ranging from a quality class 1 of highest priority to a quality class CL of lowest priority, for performing a priority control process for outputting cells of a quality class of relatively high priority in preference to cells of a quality class of relatively low priority, where each of m, n, CL is an integer of 2 or greater, comprising:
output cell buffers for the respective quality classes, associated respectively with the output highways;
a readout controller for checking the number of valid cells of cells read from the n output highways for each of the quality classes, determining a quality class c with respect to which an accumulated value of the numbers of valid cells calculated successively from quality classes of higher priority is maximum within the total number n of the output highways, generating a multiplexing control signal to instruct the output cell buffers of the quality class 1 to output n cells if the determined quality class c is the quality class 1, and checking highways corresponding to valid cells of cells read from the output cell buffers of the quality classes 2 through c and generating a multiplexing control signal to instruct writing of valid cells of the quality classes 2 through c over highways corresponding to cells which are not valid cells, of cells read from the output cell buffers of the quality class 1, if the determined quality class c is a quality class other than the quality class 1; and
a quality class multiplexer for outputting n cells read from the output cell buffers of the quality class 1 according to the multiplexing control signal or outputting a total of n cells produced by multiplexing the valid cells read from the output cell buffers of the quality classes 2 through c with n cells read from the output cell buffers of the quality class 1 based on the multiplexing control signal, to the n output highways;
whereby priority control of the quality class of relatively high priority and the quality class of relatively low priority can be carried out based on the multiplexing control signal generated by the readout controller.
The above and other objects, features and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings which illustrate examples of the present invention.